1.SCMOS observations (Page 10)

• SCMOS NOR4 circuit cell is faster than conventional CMOS
• NOR4 circuit cell, because SCMOS has faster switching time comparing to CMOS’s long discharge time.
• SCMOS logic cell is selectively added in critical path, which is part of CMOS logic circuit, to speed up the logic switching state.

2. SCMOS logic cell don’t help to overcome the time delay from interconnect parasitic RC. Answers. It does help!

• SCL has inverter drive with min. driving point impedances at  each IO net.
• No serial Tx resistors in N or P stacked paths. Which was typical for TTL nets.
• In general, SCL gates have much smaller C load for its smaller sizes compare to TTL.
• Each load is SBD instead of transistor gate pairs.
• Due to diode integration into NMOS Tx, NOR gates have smaller internal wiring load effect than NAND
• In one switching edge diode isolated the 1st stage inverter load, which has min. dimension.
• Less rail to rail swing at IO nets, and internal net only swing a distance of Vt

3. Only “OR” logic circuit can be implemented by SCMOS, therefore, SCMOS need to combine with CMOS inverter to form SCMOS’s NOR circuit.

• Basically, generic logics are NOR and NAND.
• SCMOS forms the above by OR and AND with diode tree which is biased by the asynchronous clocks. It always followed with simple inverter(s)

4. Due to wire-OR scheme, SCMOS saves layout area in multiple inputs logic cell, comparing to CMOS’s multiple inputs logic cell.

• Yes! Additionally it is access time, and power efficient for the above features listed in Q1~3.
• GSD also has many other great features and applications not disclosed.

5. The operation of 4T DSRAM is more complicate than conventional 6T SRAM. The read/write wires are treated as power line and signal line simultaneously, which degrade speed performance.

• I would say the 4T cell is unique and different from 6Tx cell. The mode of operations are not the same. People are not used to it and may not appreciate all benefits instantly.
• The advantages are 1). all peripherals are SCL which is low power and AAP efficient. Area efficiency of the 1.25V 4Tx cell improves 20%, speed and power over 50% compared CMOS using 1.8V.
• 2). The power rails are replaced by twin signal lines, that was a beauty.  However,
• 3). well- biasings are dc static. They now do not carry heavy currents,  couples little noises.
• 3a). Each of the word line segments work with bit lines delivering dynamic waveforms for proper operation. Then they all resumes to quiescent  states.
• 3b). Synchronized Word line write, WLwr, WL rd, and BLs are distributing loads in different time windows so the current surges are splittingly reduced. They all have ½ VCC swings,  ac power reduction are apparent.
• 3c). Cell read (WLrd- asserted) is enhancing storage rather than disturbing contents.
• 3d). All unselected cells are firm for WLwr- being high. Signal CL/BLb causes no harm
• 4). Performances are improved everywhere from wide input decode to SA output. Total array CBL is isolated by diodes from cell capacitors, and is shorter due to WL pitch reduction.

6. The advantage of SCMOS switching speed will be determined by R/W control operation time. All control paths for each of the operation modes can be pipelinedby SCL and Pass Transistor Logic (PTL) constructs; i.e. the fast  5 Tx Latch (1 PTx+4 Latch)) for FPGA-all by Min dimensions. There are adequate budgets and trade offs for timing controls of various R/W activities.

7. The 4T DSRAM’s bit cell stability need to study further. If cell stability is poorer than 6T SRAM, then will create yield loss in wafer manufacture. Yes! There are rooms for fine tuning the margins with respect to performances. Noise margin and speed are always trade offs.

8. SCMOS observations (Page 14) The periphery circuit of SRAM can be constructed by SCMOS logic cell, like column decoder, to speed up SRAM access time. The DC power can approach to zero, because SCMOS is a precharge low power scheme.

9. SCMOS observations (Page 17)

Summary

1. The SCMOS can be implemented in logic type circuit, like wide NOR/NAND type logic cell with faster switching speed, from circuit operation point of view.

2. Because SCMOS’s high leakage & low threshold, not recommend for analog circuit operation, which need high noise immunity & signal fidelity.

• GSD is developing other IC solutions including embedded analog,  Flash, and FPGA techniques
• Each application has its own criteria for noise and performance trade offs
• All applications can be benefited by the low power SCL/PTL implementations along AAP matrices plus Flexibility.

3. The 4T DSRAM bit cell need to be silicon proven to demonstrate its manufacturing yield, not by simulation only.

• Every hardware needs to be implemented to Si manufacturing to measure its success.
• SCMOS is for low power, high density and high performances. It will extend CMOS life cycle beyond TTL circuits.
• SCL has wide applications and shall become emerging design practice for low power UIC microelectronics.
• TSMC shall demonstrate leaderships in process development and CAE supports

Q&A 3 (from Zhou Feng)

1. Does the Schottky diode in US Pat. 4005469 fabricated in a CMOS technology?
No. It was for the Bipolar TTL Tech. owned by IBM.

Does it use Pt or Al as its anode?
That was correct.

What is the application of a Schottky diode with such a high barrier?
They serve as B-C anti-saturation clamp, preventing latch up.
The second application was decoding via biasing resistor.

2..In the top figure, we have the Optional Sub-Implant under our SBD. According to Mr. Ji at SMIC, this layer has become part of SMIC's CMOS technology, isn't it?
A I can not speak for SMIC or TSMC. However, the knowledge of making low barrier SBD were documented in the literature in the 1960, 70s.
As far as patents are concerned. IBM owned the Hi-barrier patent, and Gus Chang owns the low barrier SBD patent for the IC applications. It is enforceable if disputes for patent rights arises.  So far, no fab in the world had process flow nor spec./design rules for CMOS IC designs.

3. Can I say this layer has been widely used in sub-micron CMOS technologies?
or it is just owned by SMIC? (Page 2)
A No party has used SBD extensively in IC for microelectronics. Let me know if otherwise.
Legally, Both TSMC and SMIC has ground work performed under the request from Gus Chang. All data were confidential to both parties. They need license from me if they want to serve to public interests.

4. How did we get the chart (delay-load) on the top of this page?
A The CMOS part was from literature of 1997 IEEE paper. The SCMOS was prediction from my earlier runs. You are welcome to simulate them under 863 projects.

(Page 4)

5. Does the curves denoted with "TSMC" (CoSi2 low Schottky Barrier SBD) and the data in the table "SBD IV Characteristics - CoSi2/n-Si" come from the same experiement?  If yes, then the area of the tested schottky is 0.24um X 2.9um. The scaled IV of 1uA@0.1V for a 0.1um X 0.1um is only an estimation, isn't it? Does TSMC use 0.18um or 0.13um to make the experiement?
TSMC made 4 sets of devices of various dimensions on the test wafers. This was the first data points of feasibility study in modern microelectronics.    We are jointly develop the production technology with 0.13um Co and 0.18um Ti metals.